1. Field of the Invention
The present invention relates to a semiconductor transistor, and more particularly to a semiconductor transistor for enhancing the performance of PMOS and NMOS transistors, particularly the driving current performance, while reducing the narrow width effect.
2. Description of the Related Art
As the size of transistors is scaled down, the narrow width and reverse narrow width effects have emerged as serious problems, together with the short channel effect. Since a portion of a gate electrode generally overlaps with an isolation area, the narrow width effect is influenced by parasitic charges due to the bird's beak of an isolation layer or field stop impurities. Therefore, more charges are supplied than when a gate forms a channel of a transistor, and thus there is an advantage in that the threshold voltage of the transistor increases as a channel width becomes narrow.
In general, as the channel width of a transistor becomes narrow, a threshold voltage increases due to the narrow width effect. However, a threshold voltage may decrease depending on the manufacturing process. For example, if a field oxide layer is formed and an ion implantation is then performed with respect to the field oxide layer, impurities in a field area are distributed to have a lower density than in a channel area of a transistor. For this reason, there appears a phenomenon in which a threshold voltage increases as a channel width becomes narrow.
Further, if an isolation area is formed with LOCOS (Local Oxidation of Silicon) in a process of manufacturing a transistor with a narrow channel width, a threshold voltage generally increases. However, if an isolation area is formed through an STI (Shallow Trench Isolation), the threshold voltage decreases, and thus a current increases.
Meanwhile, if the channel lengths and widths of PMOS and NMOS transistors are adjusted to enhance their performance, the performance of one transistor is enhanced but the performance of the other transistor is deteriorated. Thus, it is important to simultaneously enhance the performance of PMOS and NMOS transistors when enhancing the performance of transistors, such as current driving performance.